1. Field of the Invention
This invention relates to electronics systems. Specifically, the present invention relates to electronic circuits.
2. Description of the Related Art
Large-scale electronic systems include a variety of sub-systems. The sub-systems may include a number of electrical boards or may include a number of components on a single board. For example, a number of chips may reside on a single board.
When several chips reside in a large-scale electronic system or sub-system, there is a need to integrate the chips with the large-scale electronic system. However, integrated circuits located in the chip may operate under different constraints than the other components in the large-scale electronic system. For the purpose of discussion, the integrated circuit in the chip is defined as an internal environment and the area of the large-scale electronic system outside of the chip is defined as an external environment. Quite often the constraints of the internal environment are different than the constraints of the external environment. For example, the internal environment may operate at a different voltage than the external environment. However, both environments may need to exchange signals and interface with each other.
Conventional electronic systems address this problem by implementing interface circuits known as pads. The pads shift the voltage level between the internal and external environment. The pads may shift the voltage level upward or the pads may shift the voltage level downward. For example, if the external environment is at a high-voltage level and the internal environment is at a low-voltage level, a pad that receives signals from the external environment will shift the voltage level of the signals downward, so that the signal will interface with the internal environment.
Conventional electronic systems implement high-voltage devices, such as transistors (i.e., Field Effect Transistors (FET(s)), to operate in the high-voltage environment. However, in conventional systems, the internal environment may be implemented with low-voltage devices. Since low-voltage devices, such as low-voltage transistors, are not designed to operate in the high-voltage environment, the low-voltage devices fail or malfunction and experience breakdown when exposed to the high-voltage environment. For example, FIG. 1 displays a conventional embodiment of a receiver 100 that shifts a voltage downward. In FIG. 1, an input signal Vin 126 is input into a first inverting pair, which consists of an nFET (i.e., n-type Field Effect Transistor) 124 and a pFET (i.e., p-type Field Effect Transistor) 128. The first inverting pair drives a second inverting pair, which includes a pFET 134 and an nFET 136. The pFET 134 and the nFET 136 are connected between ground 118 and a supply voltage 140 of 1.2 volts. The second inverting pair drives an inverter 142, which includes 1.2-volt FETs. The inverter 142 drives a node shown as 144.
The first inverting pair produces a bias-voltage output. A high_bias voltage is shown as 120 and a low_bias voltage is shown as 125. A reference signal Vref 102, the high_bias voltage 120 and the low_bias voltage 125 provide input to a reference stage. The reference stage consists of four FETs. The four FETs include nFET 104, nFET 106, pFET 108 and pFET 110. The reference stage is connected between ground 118 and a supply voltage 112. Node 109 is defined between pFET 108 and pFET 110. Node 105 is defined between nFET 104 and nFET 106.
During operation, the input signal Vin 126 is applied to the first inverting pair, which consists of nFET 124 and pFET 128. Both nFET 124 and pFET 128 are 2.5-volt FETs. A Vint signal 132 is produced as an output of the first inverting pair. The Vint signal 132 is 2.5 volts when input signal Vin 126 is input at 2.5 volts. The second inverting pair consists of nFET 136 and pFET 134, which are positioned between ground 118 and a 1.2-volt supply voltage 140. A Vshift signal 138 is generated as an output of the second inverting pair. The Vshift signal 138 is 1.2 volts. The Vshift signal 138 is inverted by the inverter 142, which is implemented with 1.2-volt FETs. The inverter 142 produces an output at node 144.
The reference stage consists of a transistor array (e.g., nFET 104, nFET 106, pFET 108 and pFET 110). The reference stage includes a reference signal Vref 102 that provides a trip point for the input signal Vin 126. The purpose of the trip point is to serve as a dividing line between a high signal (i.e., voltage) and low signal (i.e., voltage). The reference signal Vref 102 is the trip point. As a result, when input signal Vin 126 is above the reference signal Vref 102, the output of the receiver 100 is high. When input signal Vin 126 is below the reference signal Vref 102, the output of the receiver 100 is low. The reference stage biases transistors nFET 124 and pFET 128 to accomplish this task. When input signal Vin 126 is above the reference signal Vref 102, Vint signal 132 is a low signal. When input signal Vin 126 is below the reference signal Vref 102, Vint signal 132 is a high signal.
During operation, if the reference signal Vref 102 is half of the 2.5-volt supply voltage 112, nFET 106 and pFET 108 are turned on and the node 114 is set at a voltage level. The voltage level would also reside on Vset 116. As a result, when Vset 116 is applied to nFET 104 and pFET 110, there is also a voltage level on the node denoted as 109 positioned between pFET 108 and pFET 110. In addition, there is a voltage level on a node denoted as 105 positioned between nFET 104 and nFET 106.
When the reference signal Vref 102 rises relative to where the reference signal Vref 102 was initially set, pFET 108 is turned off a little more and nFET 106 is turned on a little more. In addition, the voltage on Vset 116 drops slightly. When the voltage on Vset 116 drops, pFET 110 turns on a little more and nFET 104 turns off a little more. The voltage at node 109 will rise because the impedance provided by pFET 110 is getting smaller. The impedance produced by nFET 104 is getting larger so the voltage at the node denoted by 105 is going to rise. As a result, the reference stage is used to shift the low_bias voltage 125 and the high_bias voltage 120.
When reference signal Vref 102 is set higher than average, ground (i.e., low_bias voltage 125) and the supply voltage (i.e., high_bias voltage 120) are shifted higher. When reference signal Vref 102 is shifted lower, there is higher impedance at nFET 106 and lower impedance at pFET 108 so Vset 116 is going to go a little higher. As Vset 116 starts to climb, the impedance at pFET 110 increases pushing the node 109 down, and as Vset 116 climbs, the impedance at nFET 104 gets smaller so the voltage on node 105 will fall.
There are problems with the design of the receiver 100. When input signal Vin 126 is a 3.3-volt signal and a 3.3-volt signal is applied to the gate of nFET 124, the source of nFET 124 is tied to the node 105, which is very close to ground. When input signal Vin 126 (i.e., 3.3 volts) is applied to the gate of nFET 124, nFET 124 experiences input signal Vin 126 minus the signal that is very close to ground (i.e., node 105) from its gate to its source. In other words, there is about 3.3 volts from the gate to the source of nFET 124. Since nFET 124 is a 2.5-volt FET, this violates the reliability standards for nFET 124 because nFET 124 should never have more than 2.5 volts across any two terminals. As a result, nFET 124 will experience breakdown.
Thus, there is a need for a method and apparatus for interfacing a low-voltage environment with a high-voltage environment. There is a need for a method and apparatus for receiving a high-voltage signal in an integrated circuit implemented with low-voltage devices. There is a need for a method and apparatus for configuring low-voltage devices so that they can receive and process signals from a high-voltage environment.